Transistor Resizing Approach for Full Adder Cells to Reduce the Leakage Power

Power dissipation has become a major issue it has made the way to consider the performance and area so that low power is achieved. Low power is the major requirement for portable multimedia devices employing various signal processing algorithms and architectures. Any computational circuit is incomplete without the utilization of an Adder. Addition is one of the primary operations in arithmetic circuits. We presented a new transistor resizing approach for 1bit full adder cells to regulate the optimal sleep transistor size which reduce the leakage power. In this paper, we propose approximate four bit full adder to reduce the leakage power. These four bit adders are implemented using 1 bit adder as reference. We have performed simulations using micro wind in different nano meter technologies with standard CMOS technology.